Celero Raises $275M Series C for 2nm AI Connectivity

The gap between validated silicon and dependable production is where semiconductor ambition gets expensive. Celero Communications has raised a $275M Series C to cross that gap after validating a 2nm coherent digital signal processor designed for optical links inside and between large AI data centers.

Atreides Management, Valor Equity Partners, and CapitalG co-led the September 8, 2026 financing. Sutter Hill Ventures and Maverick Silicon returned, and Atreides Managing Partner and CIO Gavin Baker will join Celero's board. The round brings Celero's company-reported total capital to $415M and values the business at more than $3B.

The money arrives less than 10 months after CapitalG led Celero's $100M Series B. That pace says investors are financing more than an attractive networking thesis. They are paying to move a difficult chip from validated architecture through R&D, product definition, qualification, manufacturing readiness, and eventually the customer systems where performance claims acquire consequences.

What Celero raised and who backed it

Celero's prior financing announcement reported $140M raised before the Series C: a $100M Series B led by CapitalG in November 2025 and $40M across earlier Seed and Series A rounds led by Sutter Hill Ventures. Valor Equity Partners, Atreides Management, Maverick Silicon, and other investors participated in those earlier rounds.

The new syndicate gives Celero three co-leads with different vantage points on scale. Atreides invests across public and private technology markets, Valor has backed capital-intensive technology businesses, and CapitalG is returning less than a year after leading the Series B. Sutter Hill's continued participation carries the relationship from Celero's earliest disclosed rounds, while Maverick Silicon remains part of the investor group.

Celero did not disclose ownership percentages, individual check sizes, security terms, or an exact valuation above the $3B threshold. The governance change it did disclose is Baker's board appointment, adding a new investor director as the company enters a more expensive operating phase.

Why optical connectivity has become an AI constraint

Accelerators create value only when they can exchange data fast enough to train and serve models as one coordinated system. As clusters expand from a rack to thousands of processors across rows, buildings, and campuses, the electrical and optical links between them become part of the performance envelope. Bandwidth density, reach, power, latency, and fiber count stop behaving like supporting details.

Celero is building coherent DSPs for that handoff. A coherent DSP processes the electrical signals entering an optical module and reconstructs optical signals after transmission, compensating for impairment while allowing more information to travel over fiber. Traditional PAM4 links can be economical at shorter distances, while conventional coherent systems were designed for telecom networks where long reach can justify additional power and cost. Celero's architecture is designed to make coherent transmission practical across more of the AI data-center network.

The company says its roadmap extends from 1.6T links to next-generation 3.2T optical interconnects across scale-up, scale-out, and scale-across networks. In plain English, Celero wants the same core technology to help connect processors inside dense systems, connect racks within large clusters, and connect workloads across data-center buildings.

What the 2nm validation proves, and what it does not

Celero says it has validated a 2nm coherent DSP that combines a purpose-built digital architecture with advanced analog technology. The milestone moves the product beyond a design file or simulation and into physical silicon, which is a meaningful risk reduction for a semiconductor startup. CapitalG says the company taped out the chip after the Series B and describes the architecture as carrying more data per link than traditional PAM4 while using less power than legacy coherent systems.

The company's broad industry first language needs context. Marvell announced 2nm coherent DSP products in March 2026, including the Electra 1.6T ZR/ZR+ chip, with customer sampling expected in the second half of 2026. Celero's defensible claim is narrower: it says it successfully validated its specific 2nm coherent DSP silicon with advanced analog technology and an architecture aimed at 1.6T through 3.2T AI interconnects.

Public validation does not yet establish manufacturing yield, customer qualification, production volume, deployment reliability, or total cost of ownership. Celero has not named customers, disclosed revenue, published independent benchmarks, identified its foundry, or provided customer-sampling and volume-production dates. Those omissions do not invalidate the milestone, but they define the proof that remains.

The founders have seen this manufacturing movie before

Nariman Yousefi and Oscar Agazzi founded Celero in 2024 after senior roles across Marvell, Inphi, Broadcom, and ClariPhy. Yousefi serves as CEO and President; Agazzi is CTO. Their backgrounds matter because coherent DSP development requires analog design, digital signal processing, system architecture, optical expertise, and the manufacturing discipline to make all of it work together.

Celero is headquartered in Irvine, California, with design centers in Canada and Argentina. Its current careers page lists roles across DSP, analog design, physical design, firmware, validation and test, applications, and product engineering. That hiring mix tracks the company's stated use of proceeds: advancing the roadmap while building the organizational muscle required for production readiness.

The advantage is experience. The exposure is that incumbents employ experienced teams too, already sell into hyperscalers and optical-module ecosystems, and know how to carry complex silicon through qualification and volume manufacturing. Celero's founders understand the course because they helped build earlier generations of it. The Series C is funding their attempt to run it on a much tighter AI infrastructure clock.

Why this round matters beyond Celero

McKinsey estimates that global data centers will require $6.7T of investment through 2030, including $5.2T for AI-related capacity. Accelerators dominate the headlines, but that capital also has to reach power, cooling, memory, switches, optical modules, fiber, and the DSPs that make high-speed optical transmission usable.

Celero's financing is one signal that investors expect optical connectivity to absorb a larger share of the AI infrastructure buildout. The bet is that coherent technology can move closer to the accelerator cluster as bandwidth rises and network distances stretch, creating room for a new architecture between short-reach PAM4 and power-hungry telecom coherent systems.

The $275M gives Celero more room to prove that thesis in silicon and prepare it for manufacturing. It also raises the standard of evidence. The next useful disclosures will be less cinematic than a valuation headline: product specifications, independent performance data, customer sampling, design wins, yield, and a production schedule that can meet the purchasing cycles of companies building the world's largest computing systems.

The next handoff is commercial

Celero has already persuaded sophisticated investors that its team, architecture, and timing deserve another large commitment. The Series C converts that conviction into engineering capacity, product work, and production preparation while the AI networking market is still being redrawn.

The company now has to make a 2nm milestone repeatable outside its own validation environment. Optical modules must work with the surrounding ecosystem, customers must qualify the product, manufacturing partners must deliver acceptable yield, and the performance advantage must survive real workloads. Celero's funding story is moving out of the financing room and into the supply chain, where every promised terabit eventually has to arrive on time.